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www.fairchildsemi.com features 8-bit data and coef?ient input precision triple 3x1 matrix-vector multiplication mode 3x3 and 5x5 two-dimensional convolution modes ttl-compatible i/o with three-state output bus offered in 68-contact plastic chip carrier (plcc) built-in 8-, 9-, and 12-bit arithmetic limiter two's complement, unsigned, or mixed data formats applications rgb to/from yuv/yiq color space conversion 3x3 or 5x5 two-dimensional fir ?tering edge enhancement and general image processing robotics and image recognition electronic darkroom desktop publishing description like the faster tmc2250, the low-cost TMC2255 can per- form a triple 3x1 matrix-vector multiplication or a 3x3 con- volution. it can also perform a 5x5 convolution with bidimensionally symmetrical coef?ients. the on-chip coef- ?ient memory stores four sets of nine 8-bit two's comple- ment coef?ients. the device accepts unsigned and/or two's complement data at 1/3 of the applied clock rate. the 3 (3x1) matrix multiply mode supports various 3-space numerical operations, such as video standards conversion (e.g. yiq to rgb) or three-dimensional perspective transfor- mation. three input ports accept the 8-bit two's complement and/or unsigned magnitude data. the two remaining input ports can be loaded with coef?ients and/or device control parameters "on-the-?." in this mode, an output is generated on every clock cycle. the 3x3 and 5x5 pixel image convolver modes support numerous functions, including static ?tering and edge detection. on every third clock cycle, the TMC2255 accepts three (3x3 mode) or ?e (5x5 mode) data inputs. in the 5x5 mode, the coef?ient kernel must be symmetric both hori- zontally and vertically. outputs from the device are gener- ated on every third clock cycle, matching the input pixel data rate, and can be limited ("clipped") to 8, 9, or 12 bits. the TMC2255 will operate at clock rates of 0 to 36 mhz over the full commercial temperature (0 c to 70 c) and sup- ply voltage ranges. logic symbol data inputs TMC2255 control inputs data outputs a 7-0 8 8 8 8 8 2 12 65-2255-01 cle cra 1-0 clk b 7-0 c 7-0 z 11-0 oe d 7-0 e 7-0 TMC2255 cmos 3 x 3, 5 x 5 image convolver 8 x 8 bits, 12 mhz data rate rev. 1.0.1
TMC2255 product specification 2 structural block diagram mpy-acc limiter 4x9x8 coefficient ram a 7-0 8 a d 20 15 rnd oe lmt clk clk/3 clk clk/3 12 12 input preaddition rounding limiting output multiplication/ accumulation 8 8 8 2 2 8 b 7-0 z 11-0 c 7-0 cle cwe cra 65-2255-02 clk d 7-0 e 7-0 cra 1-0 control functional description the TMC2255 contains an array of multipliers and adders, four 9x8-bit coef?ient "pages" and a global control block, all of which can be initialized or recon?ured through ports d and e when cle is low. device parameters include matrix coef?ient, internal device con?uration (mode), rounding precision, and input/output data formats (two's complement, unsigned, or mixed). after the control parame- ters have been loaded, device operation commences with the next clock rising edge on which cle returns high. depending on the mode selected, three or ?e data are input in parallel and proceed through a sequence of operations: input, preaddition, multiply-accumulation, rounding, lim- iting, and output. see figures 1? and the structural block diagram. input stage inputs are supplied to ports a through c in all operating modes on every third clock cycle, beginning with the clock rising edge that contains the most recent cle low-to- high transition. control and/or coef?ient parameters can be input through ports d and e during any of the three mas- ter clock cycles that make up each data cycle. in the 5x5 con- volution mode, data enter the device through ports a?. control and/or coef?ients may be updated through ports d and e on the remaining two cycles of each clock triplet. input data formats may be unsigned and/or two's comple- ment, as identi?d in the mode select ?ld of port e. preaddition in and only in 5x5 convolution, the horizontal and vertical symmetry of the coef?ient permits nine multipliers to do the work of 25. to facilitate this, the data input into ports a and e are pre-added before multiplication, as are the b and d inputs. see figure 3, the 5x5 block diagram. coef?ient memory the TMC2255 contains enough memory to store four "pages" of nine 8-bit two's complement coef?ients each. when cle is low, a new coef?ient is written through port e to the page and location address identi?d on port d. on
product specification TMC2255 3 every third clock cycle, the coef?ient page to be read and used in the immediate 3-cycle computation set is selected by cra 0 and cra 1 . of the nine coef?ients per page, k1,i (i = 1 to 3) process the port a (and e) data; k2,i, the port b and (d) data; and k3,i, the port c data. multiplication and accumulation the device computes nine products during every three clock cycles, accumulating them internally to full precision. rounding accumulated sums of products are rounded before the last 5 or 6 bits are truncated. rounding is performed by adding "010000" or "100000" to the emerging data stream, accord- ing to the desired precision of the output results. when cle = 0 and d = 0xxx1111, pin e 6 sets the chip's rounding position, viz: e 6 = 0: add .010000 and use z 0 as least signi? cant bit; e 6 = 1: add .100000 and use z 1 as least signi?ant bit, ignoring z 0 . output limiting the device provides programmable output limiting in unsigned (un) and/or two's complement (tc) format and for 8, 9, or 12 bits of output precision (including z 0 ). in 3 (3x1) mode, for an rgb-to-yiq transformation, the device can limit z 1 (y) to 9 bits unsigned while limiting z 3 (i) and z 3 (q) to 9 bits two's complement. outputs output is through the 12-bit z port, which provides 1/2 or 1 lsb precision, relative to the input format. in the 3 (3x1) mode, three outputs will appear consecutively at the z port during each triple clock cycle; for data input on clock rising edge 0, these results will emerge t do after clock rising edges 7, 8, and 9. in both convolution modes the results are output at 1/3 the device master clock rate, with the ?st point of the impulse response emerging after clock rising edge 9. to facilitate connection to a bus, the output buffers are enabled and disabled (placed in high-impedance state) by asynchro- nous control oe .
TMC2255 product specification 4 figure 1. functional block diagram, 3 (3x1) mode 8 k13 k12 k11 0 c/3 8 a 7-0 0 c/3 8 b 7-0 0 c/3 6 6, 7 8 c 7-0 8 ? 3 d 7-0 8 e 7-0 cra 1-0 cle clk clk clk/3 8 8 k21 k22 k23 k23 k32 16 16 16 16 16 16 16 18 18 18 18 16 16 k31 c/3 3 c/3 z 11-0 3 c/3 3 18 18 18 18 18 12 12 12 oe 2 we wa d in ra 6, 7, 8 7, 8, 9 4x9x8 coefficient ram 65-2255-03 round & limit
product specification TMC2255 5 figure 2. functional block diagram, 3x3 mode 8 k13 k12 k11 0 c/3 8 a 7-0 0 c/3 8 b 7-0 0 c/3 6 c/3 c/3 6, 9 8 c 7-0 8 ? 3 d 7-0 8 e 7-0 cra 1-0 cle clk clk clk/3 8 8 k21 k22 k23 k23 k32 16 16 16 16 16 16 16 18 18 18 16 16 k31 c/3 3 c/3 z 11-0 3 c/3 3 18 18 18 65-2255-04 20 20 12 12 12 oe 18 19 19 2 we wa d in ra 6, 9, 12 9, 12, 15 4x9x8 coefficient ram round & limit c/3 c/3 c/3
TMC2255 product specification 6 figure 3. functional block diagram, 5x5 mode 20 k13 k12 k11 0 c/3 8 a 7-0 8 0 c/3 8 b 7-0 0 c/3 6,9 c/3 c/3 6,9, 12 8 c 7-0 8 8 8 +3 d 7-0 e 7-0 cra 1-0 cle clk clk clk/3 9 9 8 8 8 8 k21 k22 k23 k23 k32 16 17 17 16 16 17 17 18 18 18 17 17 k31 c/3 z 11-0 3 c/3 3 c/3 3 18 19 20 20 18 18 12 12 12 oe 6 c/3 18 20 19 20 20 2 we wa d in ra 6,9,12,15,18 9,12,15,18,21 4x9x8 coefficient ram round & limit 65-2255-05 c/3 6,9, 12, 15 c/3 c/3 c/3 8 18 18 0 c/3 0 c/3 18 18
product specification TMC2255 7 pin assignments pin descriptions pin name pin number pin function description inputs clk 8 master chip clock, 0 to 30mhz. all operations are referenced to the rising edges of clk. a 0-7 , b 0-7 , c 0-7 , d 0-7 , e 0-7 5-3, 68-64; 61-54; 51-44; 43-36; 34-27 data inputs. of the device's five 8-bit data input ports, a, b, and c are used exclusively as data inputs, whereas d and e are also used to program the device (see description of cle pin). for 5x5 convolution, all five ports accept incoming data. in the other modes, only ports a-c accept incoming data, leaving d and e dedicated to control and coefficient values, which may be updated at any time. in all modes, data are loaded on every third rising edge for which cle makes a 0-to-1 transition. bits a 7 , b 7 ,?are the two's complement sign bits or most significant unsigned bitsl bits a 0 , b 0 ,?are the least significant bits (lsbs). cle 6 active-low coefficient and control load enable. when cle is low, e becomes the input port for the coefficients, and d becomes the coefficient write address and control port. when cle is high, all coefficients are held unchanged. a low-to-high transition at cle also synchronizes the TMC2255, ushering in a new data input. cra 1-0 62-63 coefficient read address. the chip can hold four "pages" of nine coefficients each. these two pins determine which of the four coefficient sets is to be used with the data entering during that cycle. the timing of coefficient selection by cra is mode dependent. in the 3 (3x1) mode, cra influences all coefficients simultaneously. in the 3x3 and 5x5 convolution modes, however, cra selects the coefficients for each multiplier column individually, i.e. three per clock cycle from left to right (see figure 3). cra should be changed only on "data input" clock cycles to avoid corrupting 3x3 or 3 (3x1) work in progress. cra should not be updated during a 5x5 operation whose result is needed. when updating coefficients on-the-fly, the user should not set cra 1-0 and d 5-4 to the same page, but should read from one page while writing to another. 1 65-2255-06 168 pin 2 3 4 6 7 8 9 10 11 12 13 14 15 16 17 5 gnd name v dd a 2 a 1 cle oe clk gnd v dd z 11 z 10 gnd z 9 z 8 z 7 v dd a 0 18 pin 19 20 21 23 24 25 26 27 28 29 30 31 32 33 34 22 gnd name z 6 z 5 z 4 z 2 z 1 z 0 gnd e 7 e 6 e 5 e 4 e 3 e 2 e 1 e 0 z 3 35 pin 36 37 38 40 41 42 43 44 45 46 47 48 49 50 51 39 gnd name d 7 d 6 d 5 d 3 d 2 d 1 d 0 c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 d 4 52 pin 53 54 55 57 58 59 60 61 62 63 64 65 66 67 68 56 gnd name v dd b 7 b 6 b 4 b 3 b 2 b 1 b 0 cra 1 cra 0 a 7 a 6 a 5 a 4 a 3 b 5
TMC2255 product specification 8 oe 7 asynchronous, active-low output enable. when oe is low, the output drivers are enabled. when oe is high, they are disabled (high-impedance). outputs z 11-0 25-19, 16-14, 12-11 data outputs. outputs available on the z port are enabled by oe . z 11 is the unsigned msb or two's complement msb/sign bit; z 1 is the integer lsb ("ones' digit"). z 0 is the 1/2 fractional digit. in the 3 (3x1) mode (e = xxxxx0xx), a new valid result will emerge t do after every rising edge of clk. in the other modes (e = xxxxx1xx), a result emerges after every third rising edge of clk. then 9- bit limiting is used, bits z 11 through z 8 will be identical. power gnd 1, 9, 13, 26, 35, 52 ground. vdd 2, 10, 17, 53 supply voltage (+5). pin descriptions (continued) pin name pin number pin function description operation and timing before operation, the TMC2255 must be initalized, i.e. loaded with coef?ients and set to the desired operating mode, data format, and rounding precision. the chip is pro- grammed via ports d and e, which double as data input ports in 5x5 mode. initialization chip select this control is accessed through bit 7 of port d. when cle is low, d 7 must be low to allow the coef?ient/control information to be updated. if d 7 is high when cle is force low, the device will not allow the coef?ient or control information to be updated, and device execution will begin or continue as commanded on the previous low-to-high transition of cle . holding d 7 high (at least when cle is low) permits the system to resynchronize the chip without changing any coef?ients or con?uration parameters. coef?ient loading when cle and d 7 are low, the coef?ient values pre- sented to port 6 are loaded into the coef?ient position and page registers selected by port d, as shown in table 1. each of the four ?ages?yy comprises a full set of nine coef?ients (one per ?ter tap). x = don? care mode selection when cle = 0 and d = 0xxx1111, pins e 2? select the chips operating mode and input data formats, as shown in table 2. table 1. coef?ient loading when d 7? = update from e 7? : coef page 0xyy0000 1,1 yy 0xyy0001 1,2 yy 0xyy0010 1,3 yy 0xyy0100 2,1 yy 0xyy0101 2,2 yy 0xyy0110 2,3 yy 0xyy1000 3,1 yy 0xyy1001 3,2 yy 0xyy1010 3,3 yy 0xxx0x11 hold all coefficients 0xxxx011 hold all coefficients 0xxx110x hold all coefficients 0xxx11x0 hold all coefficients 0xxx1111 control information 1xxxxxxx hold all coefficients
product specification TMC2255 9 rounding all computations are rounded internally following the ?al accumulation of products. rounding position depends on the output format. if the user desires outputs with 1/2 lsb preci- sion (relative to the inputs) then rounding is performed into z ? , just to the right of the lsb of the output port, z 0 . for 1 lsb precision, rounding is into z 0 , and the output is on pins z 11? only. table 3. rounding when e 7? = outputs are rounded at 00xxxxxx z 11 ? 0 (12 bits) z ? 01xxxxxx z 11 ? 1 (11 bits) z ? 1xxxxxxx unchanged from previous setting output limiting when cle = 0 and d = 0xxx1111, pins e 5? tell the chip to which numerical format(s) to limit the emerging results. unsigned (un), twos complement (tc), and mixed data formats of 8, 9, or 12 bits (including z 0 ) are supported, as shown in table 4. limit ??applies to 3x3 and 5x5 convolu- tional modes; limits z1, z2, z3 apply to 3(3x1) mode. prior to output, the limiter (if enabled) tests the leading bits of the emerging result. in the unsigned limit modes, if the msb = 1, denoting a negative value, the output is forced to 0; if the msb = 0 but any other bit above the 8, 9, or 12 bit output ?ld = 1, the output is forced to 11111111111.1. in the tc9 limit mode, values above 127.5 (00001111111.1) are forced to 00001111111.1 and values below -128 become 11110000000.0. in the tc12 limit mode, values above 1023.5 (01111111111.1) are forced to 01111111111.1, and values below -1024 become 10000000000.0. if full lsb rounding (e 6 = 1) is used, output bit z 0 is ignored, each data format is correspondingly 1 bit narrower than shown in table 4, and the .5 fractions disappear from the range limits. table 2. mode selection coefficients are always 8-bit two? complement. when e 7? = mode = data formats abc 0xxxx000 3 (3x1) mat mpy tc tc tc 0xxxx001 3 (3x1) mat mpy un tc tc 0xxxx010 reserved?o not use 0xxxx011 3 (3x1) mat mpy un un un z1 = a*k1,1 + b*k2,1 + c*k3,1 first of 3 results z2 = a*k1,2 + b*k2,2 + c*k3,2 z3 = a*k1,3 + b*k2,3 + c*k3,3 last of 3 results 0xxxx100 3x3 convolution tc tc tc 0xxxx101 3x3 convolution un un un z = a1*k1,1 + b1*k2,1 + c1*k3,1 + a2*k1,2 + b2*k2,2 + c2*k3,2 + a3*k1,3 + b3*k2,3 + c3*k3,3 0xxxx110 5x5 convolution tc tc tc 0xxxx111 5x5 convolution un un un z = a1*k1,3 + b1*k2,3 + c1*k3,3 + d1*k2,3 + e1*k1,3 + a2*k1,2 + b2*k2,2 + c2*k3,2 + d2*k2,2 + e2*k1,2 + a3*k1,1 + b3*k2,1 + c3*k3,1 + d3*k2,1 + e3*k1,1 + a4*k1,2 + b4*k2,2 + c4*k3,2 + d4*k2,2 + e4*k1,2 + a5*k1,3 + b5*k2,3 + c5*k3,3 + d5*k2,3 + e5*k1,3 1xxxxxxx unchanged from previous setting
TMC2255 product specification 10 timing result latency device operating mode affects when valid results are avail- able at the output port z 11? . the three results of a 3x1 triple dot product whose inputs enter on clock rising edge 0 will be available t do after clock rising edges 7, 8, and 9. in a 3x3 and 5x5 convolution, the ?st three impulse response points will emerge after clock rising edges 9, 12, and 15. the last two points of a 5-point response (5x5 mode) will follow after rising edges 18 and 21. instructions, inputs, and synchronization each rising edge of clk which bears a cle low-to-high transition resynchronizes the device. if cle goes from low to high on clock rising edge n, then the chip will resyn- chronize, starting a new 3-cycle sequence on that edge. it will look for incoming data at clock rising edges n+3i, where i = 1, 2, ?(see figures 4 through 10). if cle is brought low while an operation is already in progress (e.g., to update coef?ients), it should be brought high only on a regular data input clock cycle (n+3i), to avoid corrupting pending results. if cle is low, control and/or coef?ient information ene- tering on a rising edge of clk will affect all subsequent data inputs until the control parameters are again updated. inter- nal pipelining of the controls ensures that ?n progress?oper- ations on data previously input into the device will continue unaffected, as long as cle is brought high only on data input clock edges. system timing because the TMC2255s data throughput rate is 1/3 of its incoming clock rate, the user must synchronize the data inputs with the chips control inputs and internal operation. figures 4 through 7 illustrate four ways to use rising edges of cle to align data inputs in the 3 (3x1) and 3x3 modes, whereas figures 8 through 10 show how to use cle in the 5x5 mode. in figure 4, the cle 0-to-1 transition on clk rising edge 3 (t = 3) initialized the chip. the ?al con?uration and coef? cient values are loaded through ports d and e at t = 2 and the ?st incoming data enter ports a, b, and c on rising edge 6. in 3 (3x1) mode, the three results from the t = 6 input data emerge after t = 13, 14, and 15. in 3x3 mode, the ?st result from the edge 6 input data appears after edge 15 and remains until t = 18, when the second result using t = 6 inputs (which is the ?st result using t = 9 inputs) emerges. after t = 18, the convolution of the t = 6, t = 9, and t = 12 inputs, the last out- put involving the t = 6 input, appears. the part operates con- tinuously, with inputs read on every third rising clock edge and a new output available t do after each rising clock edge (3 (3x1) mode) or every third rising edge (3x3 mode). in figure 5, clk rising edges at t = 3, 6, 9, ?resynchronize the chip, with con?uration or coef?ient updates at t = 2, 5, 8, ?. data input/output timing is unchanged from figure 3. table 4. output limiting e 7? = limit z1 or z limit z2 limit z3 range (rnd = 0) 0x000xxx limiter disabled 0x001xxx un9 un9 un9 0, 255.5 0x010xxx tc12 tc12 tc12 -1024, 1023.5 0x011xxx un12 un12 un12 0, 2047.5 0x100xxx tc9 tc9 tc9 -128, 127.5 0x101xxx un9 tc9 tc9 (mixed) 0x110xxx reserved?o not use 0x111xxx un8 un8 un8 0, 127.5 1xxxxxxx unchanged from previous setting
product specification TMC2255 11 figure 4. 3 (3x1), 3x3 timing diagram, single cle rising edge figure 5. 3xx modes, periodic long cle pulses clk oe cle a 7-0 b 7-0 c 7-0 d 7-0 e 7-0 z 11-0 (3 x 1) l 2 3 6 9 12 15 18 l l1 l2 l3 m1 l1 l2+m1 65-2255-07 m2 m3 n1 l mn pq (3 x 3) z 11-0 clk oe cle a 7-0 b 7-0 c 7-0 d 7-0 e 7-0 z 11-0 (3 x 1) l 2 3 6 9 12 15 18 k l1 l2 l3 m1 l1 l2+m1 m2 m3 k l l m m n n p p q q mn pq (3 x 3) z 11-0 65-2255-08
TMC2255 product specification 12 in figure 6, clk rising edges at t = 3, 6, 9, ?again resyn- chronize the chip, but con?uration and coef?ients my be changed twice as often, at t = 1, 2, 4, 5, 7, 8, ?. in figure 7, data timing is the sames as that of figure 4. however, since cle is left low after the one-cycle initial- ization pulse, instructions and coef?ients may be updates on every clock cycle, or three times per data input. instructions entering between data values, e.g. at t = 4 or t = 5, affect the next data value (i.e., that entering at t = 6). instructions enter- ing with a given data value (e.g., t = 6) affect the next data input (i.e., at t = 9). figure 6. 3xx modes, periodic short cle pulses figure 7. 3xx modes, single cle rising edge clk oe cle a 7-0 b 7-0 c 7-0 d 7-0 e 7-0 z 11-0 (3 x 1) l 3 6 9 121518 l1 l2 l3 m1 l1 l2+m1 m2 m3 l l l l m m m m n n n n p p p p q q q q mn pq (3 x 3) z 11-0 65-2255-09 clk oe cle a 7-0 b 7-0 c 7-0 d 7-0 e 7-0 z 11-0 (3 x 1) l 3 6 9 121518 k l1 l2 l3 m1 l1 l2+m1 m2 m3 k l l l l m m m m n n n n p p p p q q q q mn pq (3 x 3) z 11-0 65-2255-10
product specification TMC2255 13 in figure 8, the clk rising edge at t = 3 synchronizes the operation. the ?al con?uration and coef?ient values are loaded through ports d and e at t = 2, and the ?st incoming data enter ports a through e at t = 6. the ?st results using the t = 6 input appears after t = 15 and remains until t = 18. the last result using the t = 6 input emerge after t = 27 and remains until t = 30. the part operates continuously, with data inputs read on every third rising edge of clk and a new output available t do after every third rising edge of clk. in figure 9, one new coef?ient or con?uration value can be input for every data input, at t = 5, 8, 11, ?. in figure 10, two new coef?ients or con?uration values can be loaded for every incoming data point, at t = 4, 5, 7, 8, 10, 11, ?. figure 8. 5x5 convolution, single cle rising edge figure 9. 5x5 convolution, periodic long cle pulse clk oe cle a 7-0 b 7-0 c 7-0 d 7-0 e 7-0 z 11-0 l 3 6 9 121518 kc l1 l2+m1 kc l l m m n n p p q q mn pq 65-2255-11 clk oe cle a 7-0 b 7-0 c 7-0 d 7-0 e 7-0 z 11-0 l 3 6 9 121518 kc l1 l2+m1 kc l l lc lc m m mc mc nc nc pc pc qc qc n n p p q q mn pq 65-2255-12
TMC2255 product specification 14 in 5x5 mode, cle should not be left low continuously, since ports d and e must serve as data inputs on every third clock cycle. if cle is low on a data input cycle, the chip will interpret the current d and e inputs as both data and instructions/coef?ients. figure 11. i/o timing diagram power-up sequence to ensure proper operation, the TMC2255 should receive at least two clock rising edges soon after power-up, with cle making a 0-to-1 transition on edge 4, 5, or 6. otherwise, some of the internal multiplexers will power up in disal- lowed states and draw excessive power. data formats figure 12 summarizes the TMC2255s data and coef?ient formats for all operating modes. although integer weighting of input data is shown, the binary point may be moved any- where to the left, as long as the binary point of the output is moved the same distance. likewise, the coef?ient binary point can be moved, as long as the output binary point is moved equally or the data input binary point is moved in the opposite direction. in all coef?ients and in all twos complement data, the most signi?ant bit carries a negative weighting. t cy 12345 t pwh t pwl 65-2255-14 t d t ho t h t s clk a, b, c, d, e cra, cle z previous new figure 10. 5x5 convolution, periodic short cle pulse clk oe cle a 7-0 b 7-0 c 7-0 d 7-0 e 7-0 z 11-0 l 3 6 9 121518 kc l1 l2+m1 kc l l lc lc lc lc m m mc mc mc mc nc nc nc nc pc pc pc pc qc qc qc qc n n p p q q mn pq 65-2255-13
product specification TMC2255 15 figure 12. data formats and bit alignment absolute maximum ratings (beyond which the device may be damaged) 1 notes: 1. absolute maximum ratings are limiting values applied individually while all other parameters are within specified operating conditions. functional operation under any of these conditions is not implied. 2. applied voltage must be current limited to specified range, and measured with respect to gnd. 3. forcing voltage must be limited to specified range. 4. current is specified as conventional current flowing into the device. parameter min typ max unit supply voltage -0.5 7.0 v input voltage -0.5 v dd + 0.5 v output applied voltage 2 -0.5 v dd + 0.5 v output forced current 3,4 -6.0 6.0 ma short circuit duration (single output in high state to ground) 1 sec operating case temperature -60 130 c junction temperature 175 c storage temperature -65 150 c lead soldering temperature (10 seconds) 300 c 2 10 data at input ports 65-2255-15 coefficients: internally accumulated products data at output port (round = 0) data at output port (round = 1) . . . . . . . . . . . . . . . . . . . . . 2 7 . . . a 7 p 16 p 13 p 8 p 7 p 6 p 5 p 4 . . . . . . z 11 z 8 z 3 z 2 z 1 z 0 . . . . . . z 11 z 8 z 3 z 2 z 1 (ignore z 0 ) p 0 k 7 k 6 k 5 k 4 k 0 a 2 a 1 a 0 2 2 2 1 2 0 2 -1 2 -2 2 -6
TMC2255 product specification 16 operating conditions electrical characteristics note: actual test conditions may vary from those shown, but guarantee operation as specified. switching characteristics parameter package min nom max unit v dd supply voltage 4.75 5.0 5.25 v v il input voltage low 0.8 v v ih input voltage high 2.0 v i ol output current low 4.0 ma i oh output current high -2.0 ma t cy cycle time TMC2255 33 ns TMC2255-1 27 t pwl clock pulse width low TMC2255 16 ns TMC2255-1 14 t pwh clock pulse width high TMC2255 13 ns TMC2255-1 10 t s input setup time TMC2255 8 ns TMC2255-1 6 t h input hold time 0 ns t a ambient temperature 0 25 70 c parameter test conditions min max unit i ddq supply current, quiescent v dd = max., v in = 0 15 ma i ddu supply current, no load v dd = max., t cy = 50ns 100 ma i il input current low -10 m a i ih input current, high 10 m a v ol output voltage, low 0.4 v v oh output voltage, high 2.0 v i os short-circuit output current -100 m a c i input capacitance 10 pf c o output capacitance 10 pf parameter test conditions package min max unit t d output delay v dd = min., c l = 25pf TMC2255 22 ns TMC2255-1 19 t ho output hold v dd = max., c l = 25pf 6 ns t ena output enable v dd = min., c l = 25pf TMC2255 18 ns TMC2255-1 15 t dis output disable v dd = min., c l = 25pf TMC2255 21 ns TMC2255-1 20
product specification TMC2255 17 equivalent circuits and transition levels figure 13. equivalent input circuit figure 14. equivalent output circuit figure 15. transition levels for three-state measurements related products tmc2011 variable length shift resistor tmc2302 image manipulation sequencer v dd p n d1 d2 gnd 65-2255-16 p well n substrate control input v dd p n p+ n+ d1 d2 gnd n substrate 65-2255-17 p well t dis 0.5v t eny 0.5v 2.0v 0.8v high impedance oexr, oeyp three-state outputs 65-2255-18
TMC2255 product specification 18 notes:
product specification TMC2255 19 mechanical dimensions ?68-lead plcc package -c- b lead coplanarity ccc c d d1 e1 e j a d3/e3 e j b1 a1 a2 a .165 .200 4.19 5.08 symbol inches min. max. min. max. millimeters notes a1 .090 .130 2.29 3.30 a2 .020 .51 b .013 .021 .33 .53 d/e .985 .995 25.02 25.27 d1/e1 .950 .958 24.13 24.33 d3/e3 .800 bsc 20.32 bsc .050 bsc 1.27 bsc e j .042 .056 1.07 1.42 2 3 nd/ne 17 17 68 68 n ccc .004 0.10 b1 .026 .032 .66 .81 notes: 1. 2. 3. all dimensions and tolerances conform to ansi y14.5m-1982 corner and edge chamfer (j) = 45 ? dimension d1 and e1 do not include mold protrusion. allowable protrusion is .101" (.25mm)
TMC2255 product specification 5/20/98 0.0m 001 stock#ds30002255 1998 fairchild semiconductor corporation life support policy fairchild? products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1 . life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2 . a critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com o r dering in f ormation p r oduct number data rate (mhz) t emperature range screening p a c k age p a c kage marking TMC2255r1c 10 0 c to 70 c commercial 68 pin plcc 2255r1c TMC2255r1c1 12.5 0 c to 70 c commercial 68 pin plcc 2255r1c1

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